There are multiple architectures or topologies for Delta-Sigma Analog-to-Digital Converters (ADCs). One such architecture uses an input feed-forward path to minimize swings on integrator outputs. In such topologies a feed-forward path feeds an ADC input to the quantizer, which is typically a so-called “sub-ADC.” This sub-ADC is typically a comparator in a single bit ADC and in a multi-bit ADC it is a flash ADC, or the like, having a number of comparators, by way of example sixteen comparators for a four bit quantizer.
FIG. 1 is a block schematic showing example prior art input feed-forward delta-sigma ADC 100. Therein, analog continuous-time voltage U(s) is fed forward to feed-forward summing circuit 102, via feed-forward path 104. Analog voltage U(s) is sampled at feed-forward sampling network 106 and delivered as a sampled discrete voltage U′(z) to so-called sub-ADC 108 (a quantizer). Analog input voltage U(s) is separately sampled by ADC sampling network 110. Feed-forward sampling network 106, ADC sampling network 110, and the like, are illustrated herein employing a switch symbol for the sake of conciseness. However, such sampling networks may include a number of components and in discrete-time input feed-forward delta-sigma ADCs may be switched-capacitor sampling circuit or networks, or the like. Regardless, sampled voltage U(z) and output of so-called sub-Digital-to-Analog Converter (sub-DAC) 112 are differentiated in ADC delta circuit 114, providing a discrete-time analog voltage at the input of discrete-time loop filter H(z) 116. The loop filter is typically a cascade of integrators with the number of integrators determining the loop order. The output voltage of discrete-time loop filter 116 is added with the sampled input signal U′(z) by summing circuit 102. Depending on the resulting voltage, the output of sub-ADC quantizer 108 is changed. Sub-DAC 112 responds on the next clock phase by changing its analog output voltage, causing discrete-time loop filter 116 to progress in the opposite direction and forcing the value of ADC digital output Y(z), to track the average value of the input U(s).
Advantageously, in such an input feed-forward topology for delta-sigma ADC, the integrators in the discrete-time loop filter 116, exhibit low voltage swings at their outputs. However, because sub-ADC 108 is directly sampling the input there is kickback (118) from the quantizer to the input U(s). Since the driving circuit generating signal U(s) has finite bandwidth and nonzero output impedance the disturbance caused by this kickback may not settle in one clock cycle. This leads to distortion of the signal being sampled by the input sampling circuit 110. Therefore, in such a delta-sigma ADC architecture with input feed-forward path, this kickback from quantizer 108 limits the distortion performance of ADC 100.